This application claims priority from German Patent Application No. 101 06 486.1, filed Feb. 13, 2001, the disclosure of which is incorporated herein by reference in its entirety.
The present invention relates to an oscillator circuit, and in particular to an oscillator circuit for a refresh timer device of a dynamic semiconductor memory.
Although they can be applied to any desired oscillator circuit, the present invention and the problems on which it is based will be explained with the aid of an oscillator circuit for a refresh timer device of a dynamic semiconductor memory.
In the case of dynamic semiconductor memories such as a DRAM, the binary information is stored in the cells as a different charge quantity. Since this charge is reduced with time by leakage currents, after expiry of a xe2x80x9crefresh timexe2x80x9d it is necessary for the information of the memory cells to be written back again. This therefore requires the generation of an oscillating clock signal for the refresh cycles and the possibility of adjusting the required refresh time.
FIG. 2 shows a schematic illustration of an oscillator circuit for the purpose of explaining the problems on which the invention is based.
In FIG. 2, T1, T2, T4, T6 denote a respective p-channel transistor device, and T3, T5 a respective n-channel transistor device, P1 and P2 a respective supply potential, 1 to 8 respective circuit nodes, Vref a reference potential, EN an activation signal, OSC an oscillator signal, Vcomp a potential at the node 6, COMP a comparator with a first input +, a second input xe2x88x92 and an output A, INV an inverter, L1 a feedback line, C and Cxe2x80x2 a respective capacitor, FU a fuse, R a resistor, and G1 an inverting AND gate with inputs E1, E2 and an output Axe2x80x2.
The node 6 is a charging/discharging node for the capacitor device consisting of two capacitors C, Cxe2x80x2, it being possible to decouple the capacitor Cxe2x80x2 by severing the fuse FU. This ability to decouple the capacitor Cxe2x80x2 or further such capacitors appended via an appropriate fuse permits fine frequency tuning.
Charging the capacitor device C, Cxe2x80x2 is performed via two component currents, specifically a first component current which is supplied by the current mirror circuit with the transistor devices T1, T2, and a second component current, which is fed via the transistor device T6 and the resistor R into the node 8 in from there into the node 6. The potential at the node 6 is applied to the comparator COMP as potential Vcomp and compared there with the reference potential Vref. The signal at the output A is either logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, depending on the comparison. This output signal A is inverted by the inverter INV and fed into the node 7. At the same time it is the oscillating output signal OSC of the oscillator circuit.
Via the feedback line L1, this signal OSC is led to the input E2 of the inverting AND gate G1, at whose other input E1 the activation signal EN is present. This activation signal EN serves, in particular, for triggering or initializing the entire circuit. Specifically, the gate G1 behaves like an inverter when the activation signal is switched from logic xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d.
The result of this is that, depending on the logic state of the signal at the node 7, either the capacitor device C, Cxe2x80x2 is charged via the two component currents, which come from the current mirror T1, T2 or from the resistor R or it is discharged via the transistor device T5.
In the first case, the transistor device T5 is turned off and the transistor devices T4, T6 are turned on, and in the second case the transistor device T5 is turned on and the transistor devices T4, TG are turned off.
This oscillator circuit is, however, susceptible to temperature fluctuations and process fluctuations, since the turn-on voltage of the transistor device T3 can be influenced strongly by these fluctuations. Consequently, the resistor R is selected in such a way that, as it were, it counteracts temperature fluctuations in the turn-on voltage of the transistor device T3. In other words, the current flowing through the resistor R is increased when the turn-on voltage of the transistor device T3 is raised, and vice versa.
The said process fluctuations can be compensated to a certain extent by tuning the capacitor device C, Cxe2x80x2. However, a grave disadvantage of this concept lies in that the temperature responses of the two component currents cannot be sensibly compensated. The oscillator frequency is thereby strongly dependent on the temperature.
The object on which the present invention is based consists in creating an improved oscillator circuit whose oscillator frequency substantially no longer exhibits a disturbing temperature response.
This object is achieved by means of the oscillator circuit specified in claim 1.
The idea on which the present invention is based resides in the fact that a current mirror circuit is present for supplying a charging current for the capacitor device, which device is connected to the charging/discharging node via first transistor device and which has a current source for supplying a substantially temperature-independent reference current. Since, in accordance with the invention, a reference current is used which is not a function of temperature, the clock frequency adjusted is constant over temperature. Neither can process fluctuations any longer come to bear.
Preferred developments are the subject matter of the subclaims.
In accordance with a preferred development, the control signal generating device has a feedback loop for feeding back the signal at the output to a control terminal of the first transistor device and to a control terminal of the second transistor device.
In accordance with a further preferred development, the capacitor device has a first and at least one second capacitor, the at least one second capacitor being connected to the first node via a fuse. Of course, a plurality of second capacitors can also be connected via a respective fuse in order thus to permit fine frequency tuning.
In accordance with a further preferred development, the feedback loop has an inverting device for inverting the signal at the output, and a feedback line for feeding back the inverted signal to the control terminal of the first transistor device and to the control terminal of the second transistor device, and the first and second transistor devices have a complementary making/breaking capacity.
In accordance with a further preferred development, the feedback loop has a first gate device with a first and a second input and an output, it being possible to feed the first input an activation signal, and the second input being connected to the feedback line, and it being possible to apply the signal at the output to the control terminal of the first transistor device and to the control terminal of the second transistor device.
In accordance with a further preferred development, the current mirror circuit has a third and a fourth transistor device whose respective first main terminals are connected to a second supply potential and whose control terminals are connected to one another, the second main terminal of the third transistor device being connected to the current source and to the interconnected control terminals, and the second main terminal of the fourth transistor device being connected to the first node via the first transistor device.
In accordance with a further preferred development, the current source can be adjusted or trimmed, and this can be achieved, for example, via trimming resistors.